Exploration of table based parasitic extraction methods (DIVA-ASSURA)

The operating speeds of electronic devices, especially the clock rate of digital chips, are limited due to capacitances of different types. The capacitances on chip can be grouped in overlap capacitances, lateral capacitances and fringe capacitances. The goal of the project, together with ADVICO and IHP Microelectronics, was the in-depth analysis of capacitances of SG2 H1 design kit structures. The in-depth analysis is based on the widely used simulation programs Diva and Assura by Comp. CADENCE.

The parasitic capacitances of 93 different structure types in three generic test cases where checked with CADENCE Diva against fieldsolver results. The total parasitic capacitances showed error plots with mean values in the range -20% up to +20%. The capacitances L1 to ground and L1 to Lx layer have error spans depending on parameter set and on chip structure types.

The test case ARRAYs above GROUNDPLANE was tested using CADENCE Assura software compared to results using the SYNOPSYS fieldsolver Raphael. Parasitic capacitance simulation of arrays above a groundplane gives chip designers good results when using CADENCE Assura.

Projektlaufzeit

18.9.2007 - 30.9.2010

Projektleitung

Kooperationspartner

  • ADVICO GmbH

Mittelgeber

IHP GmbH